ql2003 3.3v and 5.0v pasic 2 fpga combining speed, density, low cost and flexibility 3-5 ultimate verilog/vhdl silicon solution -abundant, high-speed interconnect eliminates manual routing -flexible logic cell provides high efficiency and performance -design tools produce fast, efficient verilog/vhdl synthesis speed, density, low cost and flexibility in one device -16-bit counter speeds exceeding 200 mhz -3,000 usable asic gates, 5,000 usable pld gates, 118 i/os -3-layer metal vialink process for small die sizes -100% routable and pin-out maintainable advanced logic cell and i/o capabilities -complex functions (up to 16 inputs) in a single logic cell -high synthesis gate utilization from logic cell fragments -full ieee standard jtag boundary scan capability -individually-controlled input/feedback registers and oes on all i/o pins other important family features -3.3v and 5.0v operation with low standby power -i/o pin-compatibility between different devices in the same packages -pci compliant (at 5.0v), full speed 33 mhz implementations -high design security provided by security fuses pasic 2 3 ql2003 block diagram rev. c pasic 2 highlights 3,000 usable asic gates, 118 i/o pins 192 logic cells
ql2003 3-6 the ql2003 is a 3,000 usable asic gate, 5,000 usable pld gate member of the pasic 2 family of fpgas. pasic 2 fpgas employ a unique combination of architecture, technology, and software tools to provide high speed, high usable density, low price, and flexibility in the same devices. the flexibility and speed make pasic 2 devices an efficient and high performance silicon solution for designs described using hdls such as verilog and vhdl, as well as schematics. the ql2003 contains 192 logic cells. with 118 maximum i/os, the ql2003 is available in 84-plcc, 100-pin tqfp and 144-pin tqfp packages. software support for the complete pasic families, including the ql2003, is available through three basic packages. the turnkey quick works package provides the most complete fpga software solution from design entry to logic synthesis (by synplicity, inc.), to place and route, to simulation. the quick tools tm and quick chip tm packages provide a solution for designers who use cadence, mentor, synopsys, viewlogic, veribest, or other third- party tools for design entry, synthesis, or simulation. total of 118 i/o pins - 110 bidirectional input/output pins, pci-compliant at 5.0v in -1/-2 speed grades - 4 high-drive input-only pins - 4 high-drive input/distributed network pins four low-skew (less than 0.5ns) distributed networks - two array networks available to logic cell flip-flop clock, set, and reset - each driven by an input-only pin - two global clock/control networks available to f1 logic input, and logic cell flip-flop clock, set, reset; input and i/o register clock, reset, enable; and output enable controls - each driven by an input-only pin, or any input or i/o pin, or any logic cell output or i/o cell feedback high performance - input + logic cell + output delays under 6 ns - datapath speeds exceeding 225 mhz - counter speeds over 200 mhz product summary features
ql2003 3-7 pinout diagram 84-pin plcc pasic 2 3
ql2003 3-8 pinout diagrams 100-pin tqfp pasic ql2003-1pf100c 144-pin tqfp pasic ql2003-1pf144c pin # 1 pin # 109 pin # 37 pin # 73 pin # 1 pin # 76 pin # 26 pin # 51
ql2003 3-9 100 and 144 tqfp pinout table 144 tqfp 100 tqfp function 144 tqfp 100 tqfp function 144 tqfp 100 tqfp function 144 tqfp 100 tqfp function 144 tqfp 100 tqfp function 1 2 i/o 30 nc gnd 59 nc i/o 88 60 i/o 116 82 i/o 2 nc i/o 31 nc i/o 60 43 i/o 89 61 i 117 83 i/o 3 3 i/o 32 22 i/o 61 44 i/o 90 62 aclk / i 118 nc i/o 4 4 i/o 33 nc i/o 62 45 i/o 91 63 vcc 119 84 i/o 5 nc i/o 34 23 i/o 63 nc i/o 92 64 i 120 nc i/o 6 5 i/o 35 nc i/o 64 nc i/o 93 65 gclk / i 121 nc i/o 7 nc vcc 36 24 i/o 65 46 i/o 94 66 vcc 122 85 gnd 8 6 i/o 37 25 i/o 66 nc gnd 95 67 i/o 123 nc i/o 9 nc i/o 38 26 tdi 67 nc i/o 96 nc i/o 124 86 i/o 10 7 i/o 39 27 i/o 68 nc i/o nc 68 i/o 125 87 i/o 11 nc i/o 40 28 i/o 69 47 i/o 97 nc i/o 126 88 gnd 12 nc i/o 41 29 i/o 70 48 i/o 98 69 i/o 127 89 i/o 13 8 i/o 42 nc vcc 71 49 trstb 99 nc i/o 128 90 i/o 14 nc i/o 43 30 i/o 72 50 tms 100 70 i/o 129 91 i/o 15 9 gnd 44 31 i/o 73 51 i/o 101 71 i/o 130 92 vcc 16 10 i/o 45 nc i/o 74 52 i/o 102 nc gnd 131 nc i/o 17 11 i 46 32 i/o 75 53 i/o 103 nc i/o 132 93 i/o 18 12 aclk / i 47 33 i/o 76 54 i/o 104 72 i/o 133 nc i/o 19 13 vcc 48 nc i/o 77 55 i/o 105 nc i/o 134 94 i/o 20 14 i 49 34 i/o 78 nc i/o 106 73 i/o 135 nc i/o 21 15 gclk / i 50 35 gnd 79 nc vcc 107 74 i/o 136 nc i/o 22 16 vcc 51 36 i/o 80 nc i/o 108 75 i/o 137 95 i/o 23 17 i/o 52 nc i/o 81 56 i/o 109 76 tck 138 nc gnd 24 18 i/o 53 37 i/o 82 nc i/o 110 77 stm 139 96 i/o 25 nc i/o 54 38 gnd 83 57 i/o 111 78 i/o 140 97 i/o 26 19 i/o 55 39 i/o 84 nc i/o 112 79 i/o 141 98 i/o 27 nc i/o 56 40 i/o 85 58 i/o 113 80 i/o 142 99 i/o 28 20 i/o 57 41 i/o 86 nc i/o 114 nc vcc 143 100 tdo 29 21 i/o 58 42 vcc 87 59 gnd 115 81 i/o 144 1 i/o pasic 2 3
ql2003 3-10 pin descriptions pin function description tdi test data in for jtag hold high during normal operation. connect to vcc if not used for jtag. trstb active low reset for jtag hold low during normal operation. connect to ground if not used for jtag. tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to vcc or ground if not used for jtag. tdo test data out for jtag output that must be left unc onnected if not used for jtag. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. vcc power supply pin connect to 3.3v supply. gnd ground pin connect to ground. ordering information ql 2003 - 1 pf100 c quicklogic pasic device pasic 2 device part number speed grade x = quick 0 = fast 1 = faster 2 = fastest operating range c = commercial i = industrial package code pl84 = 84-pin plcc pf100 = 100-pin tqfp pf144 = 144-pin tqfp
ql2003 3-11 absolute maximum ratings supply voltage .. -0.5 to 7.0v storage temperature.... -65 c to + 150 c input voltage . -0.5 to vcc +0.5v lead temperature ..... 300 c esd pad protection . 2000v dc input current . 20 ma latch-up immunity . 200 ma 5 volt operating range symbol parameter industrial commercial unit min max min max vcc supply voltage 4.5 5.5 4.75 5.25 v ta ambient temperature -40 85 0 70 c tc case temperature c -x speed grade 0.4 2.75 0.46 2.55 k delay factor -0 speed grade 0.4 2.00 0.46 1.85 -1 speed grade 0.4 1.61 0.46 1.50 -2 speed grade 0.4 1.35 0.46 1.25 dc characteristics over 5v operating range symbol parameter conditions min max unit vih input high voltage 2.0 v vil input low voltage 0.8 v ioh = -4 ma 3.7 v voh output high voltage ioh = -24 ma/-16 ma [1] 2.4 v ioh = -10 m a vcc-0.1 v vol output low voltage iol = 24 ma/16 ma [1] 0.45 v iol = 10 m a 0.1 v ii input leakage current vi = vcc or gnd -10 10 m a ioz 3-state output leakage current vi = vcc or gnd -10 10 m a ci input capacitance [2] 10 pf ios output short circuit current [3] vo = gnd -15 -120 ma vo = vcc 40 210 ma icc d.c. supply current [4] vi, vio = vcc or gnd 2 (typ) 10 ma notes: [1] -24 ma ioh and 24 ma iol apply only to -1/-2 commercial grade devices. these speed grades are also pci-compliant. all other devices have -16 ma ioh and 16 ma iol specifications. [2] capacitance is sample tested only. [3] only one output at a time. duration should not exceed 30 seconds. [4] for -0/-1/-2 commercial grade devices only. maximum icc is 20 ma for -x commercial grade devices and 15ma for all industrial grade devices. for ac conditions, contact quicklogic customer engineering. pasic 2 3
ql2003 3-12 3.3 volt operating range symbol parameter industrial commercial unit min max min max vcc supply voltage 3.0 3.6 3.0 3.6 v ta ambient temperature -40 85 0 70 c -0 speed grade 0.56 2.74 0.61 2.65 k delay factor -1 speed grade 0.56 2.21 0.61 2.14 -2 speed grade 0.56 1.85 0.61 1.79 dc characteristics over 3.3v operating range symbol parameter conditions min max unit vih input high voltage 2.0 v vil input low voltage 0.8 v voh output high voltage ioh = -2.4 ma 2.4 v ioh = -10 m a vcc-0.1 v vol output low voltage iol = 4 ma 0.4 v iol = 10 m a 0.1 v iih input high current sink (for tolerance to 5v devices) 5.5v > vi > vcc 12 ma ii input leakage current vi = vcc or gnd -10 10 m a ioz 3-state output leakage current vi = vcc or gnd -10 10 m a ci input capacitance [5] 10 pf ios output short circuit current [6] vo = gnd -10 -70 ma vo = vcc 25 130 ma icc d.c. supply current [7] vi, vio = vcc or gnd 0.5 (typ) 3 ma notes: [5] capacitance is sample tested only. [6] only one output at a time. duration should not exceed 30 seconds. [7] for commercial grade devices only. maximum icc is 5 ma for all industrial grade devices. for ac conditions, contact quicklogic customer engineering.
ql2003 3-13 ac characteristics at vcc = 5v, ta = 25 c (k = 1.00) propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. the ac characteristics are a design guide to provide initial timing estimates at nominal conditions. worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate delay factor, k, as specified in the delay factor table (operating range). the quick chip /quick tools /quick works software incorporates data sheet ac characteristics into the design database for precise path analysis or simulation results following place and route. logic cells input-only cells symbol parameter propagation delays (ns) fanout [8] 123481224 tin high drive input delay 2.5 2.6 2.6 2.7 3.5 4.6 5.8 tini high drive input, inverting delay 2.6 2.7 2.7 2.8 3.6 4.7 5.9 tisu input register set-up time 4.8 4.8 4.8 4.8 4.8 4.8 4.8 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.9 1.0 1.0 1.1 1.9 3.0 4.2 tlrst input register reset delay 0.8 0.9 0.9 1.0 1.8 2.9 4.1 tlesu input register clock enable set-up time 4.1 4.1 4.1 4.1 4.1 4.1 4.1 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 notes: [8] stated timing for worst case propagation delay over process variation at vcc=5.0v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [9] these limits are derived from a representative selection of the slowest paths through the pasic 2 logic cell including typical net delays . worst case delay values for specific paths should be determined from timing analysis of your particular design. symbol parameter propagation delays (ns) fanout [8] 12348 tpd combinatorial delay [9] 1.4 1.7 2.0 2.3 3.5 tsu setup time [9] 1.8 1.8 1.8 1.8 1.8 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.8 1.1 1.4 1.7 2.9 tcwhi clock high time 2.0 2.0 2.0 2.0 2.0 tcwlo clock low time 2.0 2.0 2.0 2.0 2.0 tset set delay 1.4 1.7 2.0 2.3 3.5 treset reset delay 1.2 1.5 1.8 2.1 3.3 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 pasic 2 3
ql2003 3-14 clock cells symbol parameter propagation delays (ns) loads per half column [10] 123481013 tack array clock delay 2.2 2.2 2.3 2.4 2.5 2.6 tgckp global clock pin delay 1.2 1.2 1.2 1.2 1.2 1.2 1.2 tgckb global clock buffer delay 1.5 1.6 1.6 1.7 1.8 1.9 2.0 i/o cells symbol parameter propagation delays (ns) fanout [8] 1234810 ti/o input delay (bidirectional pad) 1.8 2.1 2.4 2.7 3.9 4.6 tisu input register set-up time 4.8 4.8 4.8 4.8 4.8 4.8 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.8 1.1 1.4 1.7 2.9 3.6 tlorst input register reset delay 0.7 1.0 1.3 1.6 2.8 3.5 tlesu input register clock enable set-up time 4.1 4.1 4.1 4.1 4.1 4.1 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.6 3.0 3.6 4.1 5.2 touthl output delay high to low 2.8 3.3 3.9 4.5 5.7 tpzh output delay tri-state to high 2.1 2.6 3.1 3.7 4.8 tpzl output delay tri-state to low 2.6 3.3 4.1 4.9 6.5 tphz output delay high to tri-state [11] 2.9 tplz output delay low to tri-state [11] 3.3 notes: [10] the array distributed networks consist of 48 half columns and the global distributed networks consist of 52 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 10 loads per half column. the global clock has up to 13 loads per half column. [11] the following loads are used for tpxz: 5 pf 1k w 5 pf 1k w tphz tplz
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